Operational amplifiers (op amp) are widely used in electronic circuits to amplify signals. An op amp is adapted to receive a pair of input signals and generates either a pair of differential output signals or a single-ended output signal. FIG. 1 is a schematic diagram of a conventional differential op amp 10 that receives a pair of differential input signals IN and IP—via resistors 18 and 16—and, in response, generates a pair of differential output signals OUTN and OUTP.
Op amp 10 has only two primary inputs, INN and INP; hence it must be connected in the inverting mode, therefore, as the voltage difference between applied input signals IN and IP, respectively, swings positively, the voltage difference generated across output signals OUTN and OUTP swings negatively. Similarly, as the voltage difference between applied input signals IN and IP, respectively, swings negatively, the voltage difference generated across output signals OUTN and OUTP swings positively. Signal CM is used as the common mode voltage level of op am 10. Resistors 12, 14 are feedback resistors, that together with resistors 16, 18, are used to vary the voltage gain of op amp 10. Signals Biasp1, Biasp2 and Biasn1 are used for biasing various transistors disposed in op amp 10.
FIG. 2 is a more detailed transistor/block schematic diagram of op amp 10 having a rail to rail input range (i.e., from most positive voltage supply to the most negative voltage supply). As seen from FIG. 2, op amp 10 includes an input stage 30 and an output stage 100, each of which is described in more detail below.
FIG. 3 is a transistor schematic diagram of input stage 30 of op amp 10. Input stage 30 includes a pair of source-coupled pair amplifiers, namely source-coupled pair amplifiers 40 and 45. Source-coupled pair amplifier 40 includes NMOS transistors 32 and 34. Source-coupled pair amplifier 45 includes PMOS transistors 36 and 38. Signal D generated at the drain terminal of NMOS transistor 32 is delivered to output terminal OUTP of op amp 10 via capacitor C10 (see FIG. 2). Signal C generated at the drain terminal of NMOS transistor 34 is delivered to output terminal OUTN of op amp 10 via capacitor C5. Signal A generated at the drain terminal of PMOS transistor 36 is delivered to output terminal OUTN of op amp 10 via capacitor C20. (see FIG. 2). Signal B generated at the drain terminal of PMOS transistor 38 is delivered to output terminal OUTP of op amp 10 via capacitor C 15.
FIG. 4 is a transistor schematic diagram of a class AB (push-pull) output stage 100 of op amp 10. Output stage 100 includes, in part, a common-mode feedback circuit 150, and a pair of floating current mirrors. The first floating current mirror includes transistors 102, 104, 106, 108, 110, 112, 126 and 128. The second floating current mirror includes transistors 114, 116, 118, 120, 122 and 124, 126, 128, 130 and 132. The operation of op amp 10 is described below.
Referring to FIGS. 2, 3 and 4, source-couple pair amplifiers 40 and 45 control the voltages applied to transistors 128, 132, 126 and 130, respectively via signals A, B, C, and D by steering the flow of the current through the first and second floating current mirrors. If the voltage applied to input terminal INP is higher than that applied to input terminal INN, transistors 32 and 36 become more conductive (i.e., conduct more current) whereas transistors 34 and 38 conduct less current. This, in turn, causes transistors 116 and 110 to conduct less current, and transistors 104 and 122 to conduct more current. Consequently, transistors 130 and 128 conduct more current whereas transistors 132 and 126 conduct less current. Accordingly, output voltage signal OUTP rises and output voltage signal OUTN falls until these voltages settle at new values because of the feedback action.
If the voltage applied to input terminal INN is higher than that applied to input terminal NP, transistors 32 and 36 conduct less current whereas transistors 34 and 38 conduct more current. This, in turn, causes transistors 116 and 110 to conduct more current, and transistors 104 and 122 to conduct less current. Consequently, transistors 130 and 128 conduct less current whereas transistors 132 and 126 conduct more current. Accordingly, output voltage signal OUTN rises and output voltage signal OUTP falls until these voltages settle at new values because of the feedback action.
FIG. 5 is a transistor schematic diagram of common-mode feedback circuit (hereinafter alternatively referred to as CMFB) 150. CMFB 150 receives signals OUTP, OUTN, BIASP1, and CM, as well as supply voltages VDD, VSS. In response, CMFB 150, generates output signal FB that is applied to the gate terminals of transistors 112, and 124 (see FIG. 4). CMFB 150 includes a source-coupled pair amplifier 170, a common-mode voltage sensor 160 and a pair of diode connected transistors 158, and 156. Common-mode voltage sensor 160 includes resistors 162, 164 and capacitors 166, 168. Source-coupled pair amplifier 170 which includes PMOS transistors 152 and 154 compares the voltage signal G generated by common-mode voltage sensor 160 and that is applied to the gate terminal of PMOS transistor 152 with signal CM, and in response, generates feed-back signal FB.
If signal G has a higher voltage than signal CM, transistor 152 becomes less conductive. Therefore, voltage signal FB decreases in value. Consequently, each of transistors 110, 112, 122, and 124 conducts less current. This causes the voltages of nodes N1, N2 (see FIG. 4), which are respectively connected to the drain terminals of transistors 110 and 122 to rise. The rise in the voltage at node N1 causes transistor 128 to conduct more current. Similarly, the rise in the voltage at node N2 causes transistor 132 to conduct more current. Accordingly, output voltages OUTP and OUTN fall until their common-mode voltage becomes substantially equal to the voltage CM.
Conversely, if signal G has a lower voltage than signal CM, transistor 152 becomes more conductive. Therefore, voltage signal FB increases in value. Consequently, each of transistors 110, 112, 122, and 124 conducts more current. This causes the voltages of nodes N1, N2 to decrease. The decrease in the voltage at node N1 causes transistor 128 to conduct less current. Similarly, the decrease in the voltage at node N2 causes transistor 132 to conduct less current. Accordingly, output voltages OUTP and OUTN rise until their common-mode voltage becomes substantially equal to the voltage CM.
As seen from FIG. 1, op amp 10 must be connected in the inverting mode. An amplifier (not shown) in a previous stage and driving this inverting mode amplifier is required to drive the resistive loads 18 and 16 associated with op amp 10. A simple CMOS source-follower amplifier would face difficulty in driving the resistive load associated with op amp 10 because the output impedance of such a CMOS source-follower amplifier is often much larger than the output impedance of the relevant bipolar transistors of the previous bipolar stage. This may cause the amplitude of output signals OUTP and OUTN to exceed the desired limits. Furthermore, op amp 10 has a limited bandwidth in the inverting mode comparing to the non-inverting mode.
FIG. 6 is a block diagram of a non-inverting differential amplifier 200, as known in the prior art, that overcomes some of the problems described above in connection with op amp 10. Differential amplifier 200 receives input signals IN, and IP and includes a first single-end output operational amplifier 210, and a second single-end output operational amplifier 220. Input signal IP is applied to input terminal INP of differential amplifier 220 and input signal IN is applied to input terminal INP of differential amplifier 210. Input terminal INN of differential amplifier 210 is coupled to a first terminal of resistor 214. Input terminal INN of differential amplifier 220 is coupled to a second terminal of resistor 214. Resistors 212 and 216 couple the first and second terminal of resistor 214 to the output terminals of differential amplifier 210 and 220. Because differential amplifier 200 includes two amplifiers, namely amplifier 210, and 220, it requires more semiconductor surface area to fabricate and also consumes more power to operate.